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a
FEATURES Low Noise: 6 nV/Hz High Slew Rate: 25 V/s Wide Bandwidth: 10 MHz Low Supply Current: 2.5 mA Low Offset Voltage: 1 mV Unity Gain Stable SO-8 Package APPLICATIONS Line Driver Active Filters Fast Amplifiers Integrators GENERAL DESCRIPTION
Bipolar/JFET, Audio Operational Amplifier OP176*
PIN CONNECTIONS 8-Lead Narrow-Body SO (S Suffix)
NULL 1 -IN 2 +IN 3 V- 4 8 NC
8-Lead Epoxy DIP (P Suffix)
NULL 1 -IN 2 +IN 3 V- 4 OP-482
OP176
8 7
NC V+
OP176
7 V+ 6 OUT 5 NULL
6 OUT 5 NULL
200 V. This allows the OP176 to be used in many dc coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. The output is capable of driving 600 loads to 10 V rms while maintaining low distortion. THD + Noise at 3 V rms is a low 0.0006%. The OP176 is specified over the extended industrial (-40C to +85C) temperature range. OP176s are available in both plastic DIP and SO-8 packages. SO-8 packages are available in 2500 piece reels. Many audio amplifiers are not offered in SO-8 surface mount packages for a variety of reasons, however, the OP176 was designed so that it would offer full performance in surface mount packaging.
7
The OP176 is a low noise, high output drive op amp that features the Butler Amplifier front-end. This new front-end design combines both bipolar and JFET transistors to attain amplifiers with the accuracy and low noise performance of bipolar transistors, and the speed and sound quality of JFETs. Total Harmonic Distortion plus Noise equals previous audio amplifiers, but at much lower supply currents. Improved dc performance is also provided with bias and offset currents greatly reduced over purely bipolar designs. Input offset voltage is guaranteed at 1 mV and is typically less than
*Protected by U.S. Patent No. 5101126.
RB4 RB5 RB2 QB4 CB1 QB3 J1 2 JB1 QB2 Q3 RB1 R3 R1L QB1 Z1 CC1 R1A R1P2 1 R1S R1P1 R2P1 QB8 R2S 5 R2P2 R2L QB9 Q7 Q5 Q4 QS3 CF Q6 Q8 Q1 Z2 J2 Q2 3 Q9 CCB CC2 RB3 QB5 QB6 QB7 RB7 RB6
R4 Q10 QS1 RS1 R5 6 RS2 QS2 Q11
R2A 4
Simplified Schematic
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
OP176-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 15.0 V, T = +25C unless otherwise noted)
S A
Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Large Signal Voltage Gain
Symbol VOS VOS IB IOS VCM CMRR AVO VOS/T
Conditions
Min
Typ
Max 1 1.25 350 400 50 100 +10.5
Units mV mV nA nA nA nA V dB V/mV V/mV V/mV V/C
-40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 10.5 V, -40C TA +85C RL = 2 k RL = 2 k, -40C TA +85C RL = 600 -10.5 80 250 175 106
Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing Output Short Circuit Current POWER SUPPLY Power Supply Rejection Ratio Supply Current Supply Current Supply Voltage Range DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product AUDIO PERFORMANCE THD + Noise Voltage Noise Density Current Noise Density
Specifications subject to change without notice.
200 5
VO ISC PSRR ISY ISY VS SR GBP
RL = 2 k, -40C TA +85C RL = 600 , VS = 18 V
-13.5 -14.8 25 86 80
50 108
+13.5 +14.8
V V mA dB dB
VS = 4.5 V to 18 V -40C TA +85C VS = 4.5 V to 18 V, VO = 0 V, RL = , -40C TA +85C VS = 22 V, VO = 0 V, RL = , -40C TA +85C
2.5 4.5 15 25 10 2.75 22
mA mA V V/s MHz
RL = 2 k
en in
VIN = 3 V rms, RL = 2 k, f = 1 kHz f = 1 kHz f = 1 kHz
0.001 6 0.5
% nV/Hz pA/Hz
-2-
REV. 0
OP176 WAFER TEST LIMITS (@ V = 15.0 V, T = +25C unless otherwise noted)
S A
Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range1 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range Supply Current
Symbol VOS IB IOS VCM CMRR PSRR AVO VO ISY
Conditions VCM = 0 V VCM = 0 V VCM = 10.5 V V = 4.5 V to 18 V RL = 2 k RL = 2 k VS = 18.0 V, RL = 600 VS = 22.0 V, VO = 0 V, RL = VS = 4.5 V to 18 V, VO = 0 V, RL =
Limit 1 350 50 10.5 80 86 250 13.5 14.8 2.75 2.5
Units mV max nA max nA max V min dB min dB min V/mV min V min V min mA max mA max
NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 Guaranteed by CMR test.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V Input Voltage2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . 7.5 V Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite Storage Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature Range OP176G . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300C Package Type 8-Pin Plastic DIP (P) 8-Pin SOIC (S) JA
3
ABSOLUTE MAXIMUM RATINGS 1
DICE CHARACTERISTICS
NULL
V+
OUT
V- NULL -IN +IN
JC 43 43
Units C/W C/W
103 158
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For input voltages greater than 7.5 V limit input current to less than 5 mA. 3 JA is specified for the worst case conditions, i.e., JA is specified for device in socket for P-DIP packages; JA is specified for device soldered in circuit board for SOIC package.
OP176 Die Size 0.069 x 0.067 Inch, 4,623 Sq. Mils. Substrate (Die Backside) Is Connected to V-. Transistor Count, 26.
ORDERING GUIDE
Model OP176GP OP176GS OP176GSR OP176GBC
Temperature Range -40C to +85C -40C to +85C -40C to +85C +25C
Package Description 8-Pin Plastic DIP 8-Pin SOIC SO-8 Reel, 2500 Pieces DICE
Package Option N-8 SO-8
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP176 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-3-
OP176-Typical Characteristics
120 V = 15V S -40C T +85C A
30 V = 15V
S
100
MAXIMUM OUTPUT SWING - Volts
25
TA = +25C R = 2k
L
80 BASED ON 300 OP AMPS 60
20
15
40
10
20
5
0 0 1 2 3 t V
C
0
4
OS
5 - V/C
6
7
8
1k
10k
100k FREQUENCY - Hz
1M
10M
Figure 1. Input Offset Voltage Drift Distribution @ 15 V
16 VS = 18V, +VOM, RL = 600
Figure 4. Maximum Output Swing vs. Frequency
16 14 VS = 15V TA = +25C POSITIVE SWING
ABSOLUTE OUTPUT VOLTAGE - V
VS = 18V, -VOM, RL = 600
OUTPUT SWING - Volts
15
12 10 8 6 4 2 0 NEGATIVE SWING
14
VS = 15V, +VOM, RL = 2k VS = 15V, -VOM, RL = 2k
13
VS = 15V, +VOM, RL = 600 VS = 15V, -VOM, RL = 600
12 -50
-25
0
25
50
75
100
10
100
1k
10k
TEMPERATURE - C
LOAD RESISTANCE -
Figure 2. Output Swing vs. Temperature
300 VS = 15V V = 0V
CM
Figure 5. Maximum Output Swing vs. Load Resistance
2.50
250
INPUT BIAS CURRENT - nA
200
SUPPLY CURRENT - mA
2.25 TA = +85C 2.00 TA = +25C
150
100
1.75 TA = -40C
50
0 -50
1.50
-25 0 25 50 75 100
0
5
10
15
20
25
TEMPERATURE - C
SUPPLY VOLTAGE - V
Figure 3. Input Bias Current vs. Temperature
Figure 6. Supply Current per Amplifier vs. Supply Voltage
-4-
REV. 0
OP176
80 70 SINK 60 50 40 30 20 10 0 -50 SOURCE VS = 15V
120 T = +25C
POWER SUPPLY REJECTION - dB
ABSOLUTE OUTPUT CURRENT - mA
100
+PSRR
V = 15V
S
A
80
60
-PSRR
40
20
-25
0
25
50
75
100
0 100
1k
TEMPERATURE - C
10k FREQUENCY - Hz
100k
1M
Figure 7. Short Circuit Current vs. Temperature @ 15 V
120 100 80 GAIN 60 TA = +25C VS = 15V RL = >600
Figure 10. Power Supply Rejection vs. Frequency
2000 1750
OPEN-LOOP GAIN - V/mV
VS = 15V VO = 10V
1500 -GAIN, RL = 2k 1250 1000 750 -GAIN, RL = 600 500 250 0 -50
GAIN - dB
40 PHASE 20 0 -20 -40 -60 1k 10k 100k 1M 10M PHASE MARGIN = 60
90 135 180 225
PHASE - Degrees
+GAIN, RL = 2k
+GAIN, RL = 600 -25 0 25 50 75 100
100M
FREQUENCY - Hz
TEMPERATURE - C
Figure 8. Open-Loop Gain & Phase vs. Frequency
50 40 30 20 10 0 -10 -20 -30 1k 10k 100k 1M FREQUENCY - Hz 10M 100M TA = +25C VS = 15V
Figure 11. Open-Loop Gain vs. Temperature
40 TA = +25C VS = 15V 30
IMPEDANCE -
GAIN - dB
AV = +100 20
10
AV = +10
AV = +1 0 100 1k 10k FREQUENCY - Hz 100k 1M
Figure 9. Closed-Loop Gain vs. Frequency
Figure 12. Closed-Loop Output Impedance vs. Frequency
REV. 0
-5-
OP176
140 TA = +25C
65
VS = 15V
14 VS = 15V
100
PHASE MARGIN - Degrees
60
PHASE
12
80 60 40 20 0 100
55 GAIN
10
50
8
1k
10k FRERQUENCY - Hz
100k
1M
45 -75
-50
-25
0
25
50
75
100
6 125
TEMPERATURE - C
Figure 13. Common-Mode Rejection vs. Frequency
Figure 16. Gain Bandwidth Product & Phase Margin vs. Temperature
50
100 90 80 VS = 15V RL = 2k V
IN
= 100mVp-p
NEGATIVE SWING
40 NEGATIVE SLEW RATE
OVERSHOOT - %
70 60 50
AVCL = 1
SLEW RATE - V/s
30 POSITIVE SLEW RATE 20 V = 15V S R = 2k
L
POSITIVE SWING 40 30 20 10 0 0 100 200 300 400 500 600 700 LOAD CAPACITANCE - pF 800 900 1000
10
SWING = 10V SLEW WINDOW = 5V T = +25C
A
0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 LOAD CAPACITANCE - pF
Figure 14. Small Signal Overshoot vs. Load Capacitance
Figure 17. Slew Rate vs. Load Capacitance
35 VS = 15V RL = 2k
40 35 30 VS = 15V RL = 2k SR-
30 25
SLEW RATE - V/s
SLEW RATE - V/s
TA = +25C SR+ AND SR-
25 20 15 10 5 0 -50
SR+
20 15 10 5
0 0 0.4 0.8 1.2 1.6 DIFFERENTIAL INPUT VOLTAGE - V 2.0
-25
0
25 50 TEMPERATURE - C
75
100
Figure 15. Slew Rate vs. Differential Input Voltage
Figure 18. Slew Rate vs. Temperature
-6-
REV. 0
GAIN BANDWIDTH PRODUCT - MHz
COMMON-MODE REJECTION - dB
120
OP176
25 V = 15V T = +25C
S
2.5 VS = 15V TA = +25C
Hz
VOLTAGE NOISE - nV/
CURRENT NOISE - pA/
Hz
20
A
2.0
15
1.5
10
1.0
5
0.5
0 10 100 1k FREQUENCY - Hz 10k
0 10
100
1k FREQUENCY - Hz
10k
Figure 19. Voltage Noise Density vs. Frequency
Figure 21. Current Noise Density vs. Frequency
100 90
100 90
VOUT (50mV/DIV)
VOUT (5V/DIV)
10 0%
10 0%
50mV
TIME -100ns/DIV
100nS
5V
TIME - 500ns/DIV
500nS
Figure 20. Small Signal Transient Response
Figure 22. Large Signal Transient Response
REV. 0
-7-
OP176
APPLICATIONS Short Circuit Protection
0.1
The OP176 has been designed with output short circuit protection. The typical output drive current is 50 mA. This high output current and wide output swing combine to yield an excellent audio amplifier, even when driving large signals, at low power and in a small package.
Total Harmonic Distortion
VS = 18V RL = 600
0.010
Total Harmonic Distortion + Noise (THD + N) of the OP176 is well below 0.001% with any load down to 600 . However, this is dependent upon the peak output swing. In Figure 23 it is seen that the THD + Noise with 3 V rms output is below 0.001%. In the following Figure 24, THD + Noise is below 0.001% for the 10 k and 2 k loads but increases to above 0.01% for the 600 load condition. This is a result of the output swing capability of the OP176. Notice the results in Figure 25, showing THD vs. VIN (V rms).
0.1
10Vrms 5Vrms 0.001 3Vrms 1Vrms
.0001 20
100
1k
10k
20k
Figure 25. THD + Noise vs. Output Amplitude (V rms)
VS = 15V VO = 3Vrms
0.010
The output of the OP176 is designed to maintain low harmonic distortion while driving 600 loads. However, driving 600 loads with very high output swings results in higher distortion if clipping occurs. To attain low harmonic distortion with large output swings, supply voltages may be increased. Figure 26 shows the performance of the OP176 driving 600 loads with supply voltages varying from 18 volts to 20 volts. Notice that with 18 volt supplies the distortion is fairly high, while with 20 volt supplies it is a very low 0.0007%.
0.001
600
0.1
.0001 20
100
1k
10k
20k
RL = 600
FIGURE 23. THD + Noise vs. Frequency
0.010
0.1
VO = 18V
VS = 18V VO = 10Vrms
0.001
0.010
VO = 19V VO = 20V
VO = 22V
0.001 600
0.0001 20
100
1k
10k
20k
10k 2k
Figure 26. THD + Noise vs. Supply Voltage
0.0001 20 100 1k 10k 20k
Figure 24. THD + Noise vs. RLOAD
-8-
REV. 0
OP176
Noise
The voltage noise density of the OP176 is below 6 nV/Hz from 30 Hz. This enables low noise designs to have good performance throughout the full audio range. Figure 27 shows a typical OP176 with a 1/f corner at 6 Hz.
CH A: 80.0 V FS MKR: 15.9 V/ Hz 10.0 V /DIV
If the original 5534 socket includes offset nulling circuitry, one would find a 10 k to 100 k potentiometer connected between Pins 1 and 8 with said potentiometer's wiper arm connected to V+. In order to upgrade the socket to the OP176, this circuit should be removed before inserting the OP176 for its offset nulling scheme uses Pins 1 and 5. Whereas the wiper arm of the 5534 trimming potentiometer is connected to the positive supply, the OP176's wiper arm is connected to the negative supply. Directly substituting the OP176 into the original socket would inject a large current imbalance into its input stage. In this case, the potentiometer should be removed altogether, or, if nulling is still required, the trimming potentiometer should be rewired to match the nulling circuit as illustrated in Figure 29.
+VS
\ 0 Hz MKR:
5.4 Hz
BW:
50Hz / 300 mHz
2
7 6 5 VOUT
OP176
Figure 27. 1/f Noise Corner
Noise Testing
3 1 4 P1
For audio applications the noise density is usually the most important noise parameter. For characterization the OP176 is tested using an Audio Precision, System One. The input signal to the Audio Precision must be amplified enough to measure accurately. For the OP176 the noise is gained by approximately 1020 using the circuit shown in Figure 28. Any readings on the Audio Precision must then be divided by the gain. In implementing this test fixture, good supply bypassing is essential.
-VS
P1 = 10k VOS TRIM RANGE = 2mV
Figure 29. Offset Voltage Nulling Scheme
Input Overcurrent Protection
OP176 OP37 OP37 100 909 100 909 490 4.42k OUTPUT
Figure 28. Noise Test
Upgrading "5534`' Sockets
The OP176 is a superior amplifier for upgrading existing designs using the industry standard 5534. In most application circuits, the OP176 can directly replace the 5534 without any modifications to the surrounding circuitry. Like the 5534, the OP176 follows the industry standard, single op amp pinout. The difference between these two devices is the location of the null pins and the 5534's compensation capacitor. The 5534 normally requires a 22 pF capacitor between Pins 5 and 8 for stable operation. Since the OP176 is internally compensated for unity gain operation, it does not require external compensation. Nevertheless, if the 5534 socket already includes a capacitor, the OP176 can be inserted without removing it. Since the OP176's Pin 8 is a "NO CONNECT'' pin, there is no internal connection to that pin. Thus, the 22 pF capacitor would be electrically connected through Pin 5 to the internal nulling circuitry. With the other end left open, the capacitor should have no effect on the circuit. However, to avoid altogether any possibility for noise injection, it is recommended that the 22 pF capacitor be cut out of the circuit entirely. REV. 0 -9-
The maximum input differential voltage that can be applied to the OP176 is determined by a pair of internal Zener diodes connected across its inputs. They limit the maximum differential input voltage to 7.5 V. This is to prevent emitter-base junction breakdown from occurring in the input stage of the OP176 when very large differential voltages are applied. However, in order to preserve the OP176's low input noise voltage, internal resistances in series with the inputs were not used to limit the current in the clamp diodes. In small signal applications, this is not an issue; however, in applications where large differential voltages can be inadvertently applied to the device, large transient currents can flow through these diodes. Although these diodes have been designed to carry a current of 5 mA, external resistors as shown in Figure 30 should be used in the event that the OP176's differential voltage were to exceed 7.5 V.
1.4k
2
- OP176 6
1.4k
3
+
Figure 30. Input Overcurrent Protection
OP176
Output Voltage Phase Reversal
+15V 10F + 0.1F
Since the OP176's input stage combines bipolar transistors for low noise and p-channel JFETs for high speed performance, the output voltage of the OP176 may exhibit phase reversal if either of its inputs exceeds the specified negative common-mode input voltage. This might occur in some applications where a transducer, or a system, fault might apply very large voltages upon the inputs of the OP176. Even though the input voltage range of the OP176 is 10.5 V, an input voltage of approximately -13.5 V will cause output voltage phase reversal. In inverting amplifier configurations, the OP176's internal 7.5 V clamping diodes will prevent phase reversal; however, they will not prevent this effect from occurring in noninverting applications. For these applications, the fix is a 3.92 k resistor in series with the noninverting input of the device and is illustrated in Figure 31.
R FB*
2 VIN
7
3
OP176
4
6 RL 2k
VOUT
0.1F
10F
-15V
V IN R S 3.92k
2 3
OP176
6 R L
V OUT
Figure 33. Unity Gain Follower
+15V 10F + 0.1F
2k
*R FB IS OPTIONAL
10pF
Figure 31. Output Voltage Phase Reversal Fix
Overdrive Recovery
VIN
4.99k 4.99k 2 7 6 2k 0.1F VOUT
The overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to a rated output level from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large abnormal transient event. The circuit shown in Figure 32 was used to evaluate the OP176's overload recovery time. The OP176 takes approximately 1 s to recover to VOUT = +10 V and approximately 900 ns to recover to VOUT = -10 V.
R1 1k 2 3 OP176 V IN 4Vp-p @ 100Hz RS 909 6 R2 10k
3 2.49k
OP176
4
10F + -15V
Figure 34. Unity Gain Inverter
V OUT RL 2.43k
Figure 32. Overload Recovery Time Test Circuit
High Speed Operation
In inverting and noninverting applications, the feedback resistance forms a pole with the source resistance and capacitance (RS and CS) and the OP176's input capacitance (CIN), as shown in Figure 35. With RS and RF in the k range, this pole can create excess phase shift and even oscillation. A small capacitor, CFB, in parallel with RFB eliminates this problem. By setting RS (CS + CIN) = RFB CFB, the effect of the feedback pole is completely removed.
CFB
As with most high speed amplifiers, care should be taken with supply decoupling, lead dress, and component placement. Recommended circuit configurations for inverting and noninverting applications are shown in Figure 33 and Figure 34.
RS CS
RFB
VOUT CIN
Figure 35. Compensating the Feedback Pole
-10-
REV. 0
OP176
Attention to Source Impedances Minimizes Distortion
RG VIN RF CF RX
Since the OP176 is a very low distortion amplifier, careful attention should be given to source impedances seen by both inputs. As with many FET-type amplifiers, the p-channel JFETs in the OP176's input stage exhibit a gate-to-source capacitance that varies with the applied input voltage. In an inverting configuration, the inverting input is held at a virtual ground and, as such, does not vary with input voltage. Thus, since the gate-to-source voltage is constant, there is no distortion due to input capacitance modulation. In noninverting applications, however, the gate-to-source voltage is not constant. The resulting capacitance modulation can cause distortion above 1 kHz if the input impedance is > 2 k and unbalanced. Figure 36 shows some guidelines for maximizing the distortion performance of the OP176 in noninverting applications. The best way to prevent unwanted distortion is to ensure that the parallel combination of the feedback and gain setting resistors (R F and RG) is less than 2 k. Keeping the values of these resistors small has the added benefits of reducing the thermal noise of the circuit and dc offset errors. If the parallel combination of R F and RG is larger than 2 k, then an additional resistor, R S, should be used in series with the noninverting
RG RF
OP176
CL
VOUT
RX = RO RG WHERE RO = OPEN-LOOP OUTPUT RESISTANCE RF
CF =
[ I + ( | AI
CL|
)] (
RF + RG RF
) CL RO
Figure 37. In-the-Loop Compensation Technique for Driving Capacitive Loads
APPLICATIONS USING THE OP176 A High Speed, Low Noise Differential Line Driver
RS* VIN
OP176
VOUT * RS = RG//RF IF RG//RF > 2k FOR MINIMUM DISTORTION
Figure 36. Balanced Input Impedance to Mininize Distortion in Noninverting Amplifier Circuits
The circuit of Figure 38 is a unique line driver widely used in many applications. With 18 V supplies, this line driver can deliver a differential signal of 30 V p-p into a 2.5 k load. The high slew rate and wide bandwidth of the OP176 combine to yield a full power bandwidth of 130 kHz while the low noise front end produces a referred-to-input noise voltage spectral density of 15 nV/Hz. The circuit is capable of driving lower impedance loads as well. For example, with a reduced output level of 5 V rms (14 V p-p), the circuit exhibits a full-power bandwidth of 190 kHz while driving a differential load of 249 ! The design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount importance. Like the transformer-based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily set for noninverting, inverting, or differential operation.
R3 2k 2 3 A2 6 R7 2k R4 2k A1 6 P1 10k R5 2k R6 2k 2 3 A3 6 R8 2k R10 50 R12 1k VO2 R9 50 VO1 R11 1k
input. The value of R S is determined by the parallel combination of R F and RG to maintain the low distortion performance of the OP176. For a more generalized treatment on circuit impedances and their effects on circuit distortion, please review the section on Active Filters at the end of the Applications section.
Driving Capacitive Loads
R1 2k VIN 3 2
As with any high speed amplifier, care must be taken when driving capacitive loads. The graph in Figure 14 shows the OP176's overshoot versus capacitive load. The test circuit is a standard noninverting voltage follower; it is this configuration that places the most demand on an amplifier's stability. For capacitive loads greater than 400 pF, overshoot exceeds 40% and is roughly equivalent to a 45 phase margin. If the application requires the OP176 to drive loads larger than 400 pF, then external compensation should be used. Figure 37 shows a simple circuit which uses an in-the-loop compensation technique that allows the OP176 to drive any capacitive load. The equations in the figure allow optimization of the output resistor, RX, and the feedback capacitor, CF, for optimal circuit stability. One important note is that the circuit bandwidth is reduced by the feedback capacitor, CF, and is given by:
BW = 1 2 R F CF
VO2 - VO1 = VIN
R2 2k
A1, A2, A3 = OP176 GAIN = R3
R1
SET R2, R4, R5 = R1 AND R6, R7, R8 = R3
Figure 38. A High Speed, Low Noise Differential Line Driver
REV. 0
-11-
OP176
A Low Noise Microphone Preamplifier with a Phantom Power Option
1.0 VS = 18V 80kHz LPF
Figure 39 is an example of a circuit that combines the strengths of the SSM2017 and the OP176 into a variable gain microphone preamplifier with an optional phantom power feature. The SSM2017's strengths lie in its low noise and distortion, and gain flexibility/simplicity. However, rated only for 2 k or higher loads, this makes driving 600 loads somewhat limited with the SSM2017 alone. A pair of OP176s are used in the circuit as a high current output buffer (U2) and a DC servo stage (U3). The OP176's high output current drive capability provides a high level drive into 600 loads when operating from 18 V supplies. For a complete treatment of the circuit design details, the interested reader should consult application note AN-242, available from Analog Devices. This amplifier's performance is quite good over programmed gain ranges of 2 to 2000. For a typical audio load of 600 , THD + N at various gains and an output level of 10 V rms is illustrated in Figure 40. For all but the very highest gain, the THD + N is consistent and well below 0.01%, while the gain of 2000 becomes more limited by noise. The noise performance of the circuit is exceptional with a referred-to-input noise voltage spectral density of 1 nV/Hz at a circuit gain of 1000.
0.1
G = 2000
0.010
G = 200
G=4 0.001 G = 20
20
100
1k
10k
20k
Figure 40. Low Noise Microphone Preamplifier THD + N Performance at Various Gains (VOUT = 10 V rms and RL = 600 )
+48V C8 47F/ 63V
+
+VS R10 100 R8 6.81k Z1 Z2 C5 33pF R2 20k -VS 2 3 7 R4 221k 4 6 R7 1k U2 OP176 -VS PHANTOM POWER SUPPLY CONNECTIONS, INTERLOCKED WITH +/-VS (SEE NOTE 5). C6 0.1F
+18V
+
C3 100F/25V
R9 6.81k
C7 0.1F
+ C4
100F/25V -18V
1) -IN TO MICROPHONE COMMON
+
CIN1 RP1 47F/ 49.9 63V RB1 10k CN 4.7nF/ FILM RB2 10k 2200F/ 10V
+
+VS U1 CRF2 SSM2017P 100pF 3 81 2 CRF1 100pF -VS 4 5 7 6 R1 10k
CG1 RG 3)
R3 49.9 OUTPUT
+
CG2
+IN
+
CIN2 RP2 47F/ 49.9 63V Z3
2200F/ 10V Z4
R6 10k
+VS C1 1F FILM U3 OP176 +V S
OUT COMMON
D1 D2 1N458 1N458
NOTES: 1) Z1-Z4 1N752 (SEE TEXT). 2) CINX, CGX LOW LEAKAGE ELECTROLYTIC TYPES (SEE TEXT). 3) GAIN = G = 2 x ((10k/RG ) +1) (SEE TEXT). 4) ALL RESISTORS 1% METAL FILM. 5) DOTTED PHANTOM POWER RELATED COMPONENTS OPTIONAL (SEE TEXT).
7 6
2 3
R5 221k
4 -VS C2 1F FILM
Figure 39. A Low Noise Microphone Preamplifier
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REV. 0
OP176
A Low Noise, +5 V/+10 V Reference A Differential ADC Driver
In many high resolution applications, voltage reference noise can be a major contributor to overall system error. Monolithic voltage references often exhibit too much wide band noise to be used alone in these systems. Only through careful filtering and buffering of these monolithic references can one realize wideband microvolt noise levels. The circuit illustrated in Figure 41 is an example of a low noise precision reference optimized for both ac and dc performance around the OP176. With a +10 V reference (the AD587), the circuit exhibits a 1 kHz spot output noise spectral density < 10 nV/Hz. The reference output voltage is selectable between 5 V and 10 V, depending only on the selection of the monolithic reference. The output table illustrated in the figure provides a selection of monolithic references compatible with this circuit.
OUTPUT TABLE VOUT 10V 10V 10V 10V 5V 5V 5V 5V U1 AD587 REF01 REF10 AD581 REF195 AD586 REF02 REF05 TOLERANCE (+/-mV) 5 TO 10 30 TO 100 30 TO 50 5 TO 30 2 TO 10 2.5 TO 20 15 TO 50 15 TO 25 U2 OP176 7 2 8 U1 4 C4 0.1F 6 5 R2 10k RTRIM 10k (OPTIONAL) C1 100F/25V C2 100F/25V R5 1.1k C5 10F/25V R1 1k R3 100 3 6 4 2 R6 3.3
High performance audio sigma-delta ADCs, such as the stereo 16-bit AD1878 and the 18-bit AD1879, present challenging design problems with regards to input interfacing. Because of an internal switched capacitor input circuit, the ADC input structure presents a difficult dynamic load to the drive amplifier with fast transient input currents due to their 3 MHz ADC sampling rate. Also, these ADCs inputs are differential with a rated full-scale range of 6.3 V, or about 4.4 V rms. Hence, the ADC interface circuit of Figure 42 is designed to accept a balanced input signal to drive the low dynamic impedances seen at the inputs of these ADCs. The circuit uses two OP176
+VS TO U1, U2 C1 100pF R2 BALANCED INPUTS (+) 5.62k R1 5.76k U1 U1, U2 = OP176 C2 100pF R4 5.62k R3 5.49k U2 (+) 5k R6 51 C5 0.01F C3 0.0047F -VS R5 51 C4 0.01F 0.1F
+12V ANALOG 100/25V COM 100/25V -12V ANALOG
0.1F
R4 100 C3 100F/25V
VOUT
(-)
+15V
TO VIN - AD1878/ AD1879 SIGMADELTA ADC VIN + L & R INPUTS
= AG, PIN 10 OR 18
5k
REF COMMON
USE FOR SINGLE-ENDED INPUTS
NOTES C1-C5 = NPO CERAMIC, NON-INDUCTIVE, C3-C5 CLOSE TO ADC R1-R6 = 1% METAL FILM
Figure 41. A Low Noise, +5 V/+10 V Reference Figure 42. A Balanced Driver Circuit for Sigma-Delta ADCs
In operation, the basic reference voltage is set by U1, either a 5 V or 10 V 3-terminal reference chosen from the table. In this case, the reference used is a 10 V buried Zener reference, but all U1 IC types shown can plug into the pinout and can be optionally trimmed. The stable 10 V from the reference is then applied to the R1-C1-C2 noise filter, which uses electrolytic capacitors for a low corner frequency. When electrolytic capacitors are used for filtering, one must be cognizant of their dc leakage current errors. Here, however, a dc bootstrap of C1 is used, so this capacitor sees only the small R2 dc drop as bias, effectively lowering its leakage current to negligible levels. The resulting low noise, dc-accurate output of the filter is then buffered by a low noise, unity gain op amp using an OP176. With the OP176's low VOS and control of the source resistances, the dc performance of this circuit is quite good and will not compromise voltage reference accuracy and/or drift. Also, the OP176 has a typical current limit of 50 mA, so it can provide higher output currents when compared to a typical IC reference alone.
amplifiers as inverting low-pass filters for their speed and high output current drive. The outputs of the OP176s then drive the differential ADC inputs through an RC network. This RC network buffers the amplifiers against step changes at the ADC sampling inputs using one differential (C3) and two commonmode connected capacitors (C4 and C5). The 51 series resistors isolate the OP176s from the heavily capacitive loads, while the capacitors absorb the transient currents. Operating on 12 V supplies, this circuit exhibits a very low THD + N of 0.001% at 5 V rms outputs. For single-ended drive sources, a third op amp unity gain inverter can be added between R2's (+) input terminal and R4. For best results, short-lead, noninductive capacitors are suggested for C3, C4, and C5 (which are placed close to the ADC), and 1% metal-film types for R1 through R6. For surface mount PCBs, these components can be NPO ceramic chip capacitors and thin-film chip resistors.
REV. 0
-13-
OP176
An RIAA Phono Preamp
Figure 43 illustrates a simple phono preamplifier using RIAA equalization. The OP176 is used here to provide gain and is chosen for its low input voltage noise and high speed performance. The feedback equalization network (R1, R2, C1, and C2) forms a three time constant network, providing reasonably accurate equalization with standard component values. The input components terminate a moving magnet phono cartridge as recommended by the manufacturer, the element values shown being typical. When this ac coupled circuit is built with a low noise bipolar input device such as the OP176, amplifier bias current makes direct cartridge coupling difficult. This circuit uses input and output capacitor coupling to minimize biasing interactions. Input ac coupling to the amplifier is provided via C5, and the low frequency termination resistance, RT, is the parallel equivalent of R6 and R7. R3 of the feedback network is ac grounded via C4, a large value electrolytic. Additionally, this resistor is set to a low value to minimize circuit noise from nonamplifier sources. These design measures reduce the dc offset at the output of the OP176 to a few millivolts. The output coupling network of C3 and R4 is shown as suitable for wide band response, but it can be set to a 7950 s time constant for use as a 20 Hz rumble filter. The 1 kHz gain ("G") of this circuit, controlled by R3, is calculated as:
G (@ 1 kHz) = 0.101 x 1 + R1 R3
parasitics. One percent metal-film resistors and two percent film capacitors of polystyrene or polypropylene are recommended. Using the suggested values, the frequency response relative to the ideal RIAA characteristic is within 0.2 dB over 20 Hz-20 kHz. Even tighter response can be achieved by using the alternate values, shown in brackets "[ ]," with the trade-off of a non off-the-shelf part. As previously mentioned, the OP176 was chosen for three reasons: (1) For optimal circuit noise performance, the amplifier used should exhibit voltage and current noise densities of 5 nV/Hz and 1 pA/Hz, respectively. (2) For high gain accuracy, especially at high stage gains, the amplifier should exhibit a gain bandwidth product in excess of 5 MHz. (3) Equally important because of the 100% feedback through the network at high frequencies, the amplifier must be unity gain stable. With the OP176, the circuit exhibits low distortion over the entire range, generally well below 0.01% at outputs levels of 5 V rms using 18 V supplies. To achieve maximum performance from this high gain, low level circuit, power supplies should be well regulated and noise free, and care should be taken with shielding and conductor layout.
Active Filter Circuits Using the OP176
For an R3 of 200 , the circuit gain is just under 50 x ( 34 dB), and higher gains are possible by decreasing R3. For any value of R3, the R5-C6 time constant should be equal to R3 and the series equivalent of C1 and C2. Using readily available standard values for network elements (R1, R2, C1, and C2) makes the design easily reproducible and inexpensive. These components are ideally high quality precision types, for low equalization errors and minimum
A general active filter topology that lends itself to both high-pass (HP) and low-pass (LP) filters is the well known Sallen-Key (SK) VCVS (Voltage-Controlled, Voltage Source) architecture. This filter type uses the op amp as a fixed gain voltage follower at either unity or a higher gain. Discussed here are simplified 2pole, unity gain forms of these filters, which are attractive for several reasons: One, at audio frequencies, using an amplifier with a 10 MHz bandwidth such as the OP176, these filters exhibit reasonably low sensitivities for unity gain and high damping (low Q). Second, as voltage followers, they are also inherently gain accurate within their pass band; hence, no gain resistor scaling errors are generated. Third, they can also be made "dc accurate," with output dc errors of only a few millivolts. The specific filter response in terms of HP, LP and damping is determined by the RC network around the op amp, as shown in Figure 44a.
+VS 0.1F 0.1F MOVING MAGNET PICKUP -VS C3 100F/25V C1 0.03F 2% R2 8.25k 1% [7.87k] R3 C4 1000F/16V C2 0.01F 2% R4 100k 100F 100F
+18V
C5 100F/25V 3 Ct 150pF R7 100k
+VS 7 U1 OP176 2 4 -VS 6
-18V
R5 499 VOUT
R6 100k
Rt = R6| |R7 ~ - 50k
R1 100k 1% [97.6k ]
200 (34dB) 100 (40dB)
C6 3nF
Figure 43. An RIAA Phono Preamplifier Circuit
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REV. 0
OP176
High Pass Sections Low Pass Sections
Figure 44a illustrates the high-pass form of a 2-pole SK filter using an OP176. For simplicity and practicality, capacitors C1 and C2 are set equal ("C"), and resistors R2 and R1 are adjusted to a ratio, N, which provides the filter damping coefficient, , as per the design expressions. This high pass design is begun with selection of standard capacitor values for C1 and C2 and a calculation of N. The values for R1 and R2 are then determined from the following expressions:
R1 =
and
1 2 x FREQ x C x N
R2 = N x R1
In the LP SK arrangement of Figure 44b, the R and C elements are interchanged where the resistors are made equal. Here, the ratio of C2/C1 ("M") is used to set the filter , as noted. Otherwise, this filter is similar to the HP section, and the resulting 1 kHz LP response is shown in Figure 45. The design begins with a choice of a standard capacitor value for C1 and a calculation of M. This then forces a value of "M x C1" for C2. Then, the value for R1 and R2 ("R") is calculated according to the following equation:
R=
1 2 x FREQ x C1 x M
IN
IN C1 0.01F C2 0.01F R1 11k (11.254k) +VS 7 6 OUT GIVEN: , FREQ SET C1 = C2 = C
OUT R1 11k (11.254k) R2 11k (11.254k) C2 0.01F C1 0.02F GIVEN: , FREQ
OP176
3 2
+VS 7 6
=
OP176
3 R2 22k (22.508k) 2
= 2
N=
N 4
=
4 -VS
2
1 Q R2 = R1 N
4 -VS
1 =Q C2 M= = C1 2 2 M 4
CHOOSE C1 C2 = M x C1 R= 1 2 FREQ x C1 x M
R1 =
1 2 FREQ x C x
R2 = N x R1 ZCOMP ZCOMP (HIGH PASS) IN (-) R2 C2 C1 R1 OUTPUT 1 kHz BW SHOWN
ZCOMP ZCOMP (LOW PASS) IN (-) C2 R2 R1 C1 OUTPUT
1 kHz BW SHOWN
Figures 44b. Two-Pole Unity Gain HP/LP Active Filters Figures 44a. Two-Pole Unity Gain HP/LP Active Filters
In this examples, circuit (or 1/Q) is set equal to 2, providing a Butterworth (maximally flat) characteristic. The filter corner frequency is normalized to 1 kHz, with resistor values shown in both rounded and (exact) form. Various other 2-pole response shapes are possible with appropriate selection of , and frequency can be easily scaled, using inversely proportional R or C values for a given . The 22 V/s slew rate of the OP176 will support 20 V p-p outputs above 100 kHz with low distortion. The frequency response resulting with this filter is shown as the dotted HP portion of Figure 45.
10.000 LP 0.0 HP -10.00 -20.00
dBr
-30.00 -40.00 -50.00 -60.00 -70.00 20 100 1k FREQUENCY - Hz 10k 50k
Figure 45. Relative Frequency Response of 2-Pole, 1 kHz Butterworth LP (Left) and HP (Right) Active Filters
REV. 0
-15-
OP176
Passive Component Selection for Active Filters
1
THD +N - %
The passive components suitable for active filters deserve more than casual attention. Resistors should be 1%, low TC, metalfilm types of the RN55 or RN60 style. Capacitors should be 1% or 2% film types preferably, such as polypropylene or polystyrene, or NPO (COG) ceramic for smaller values.
Active Filter Circuit Subtleties
0.1
B1 0.010
In designing active filter circuits with the OP176, moderately low values (10 k or less) for R1 and R2 can be used to minimize the effects of Johnson noise when critical. The practical tradeoff is, of course, capacitor size and expense. DC errors will result for larger values of resistance, unless compensation for amplifier input bias current is used. To add bias compensation in the HP filter section of Figure 42a, a feedback compensation resistor equal to R2 can be used. This will minimize bias current induced offset to the product of the OP176's IOS and R2. For an R2 of 25 k, this produces a typical compensated offset voltage of 50 V. Similar compensation is applied to Figure 42b, using a resistance equal to R1+ R2. Using dc compensation, filter output dc errors using the OP176 will be dominated by its VOS, which is typically 1 mV or less. A caveat here is that the additional resistors can increase noise substantially. For example, a 10 k resistor generates ~ 12 nV/ Hz of noise and is about twice that of the OP176. These resistors can be ac bypassed to eliminate their noise using a simple shunt capacitor chosen such that its reactance (XC) is much less than R at the lowest frequency of interest. A more subtle form of ac degradation is also possible in these filters, namely nonlinear input capacitance modulation. This issue was previously covered for general cases in the section on minimizing distortion. In active filter circuits, a fully compensating network (for both dc and ac performance) can be used to minimize this distortion. To be most effective, this network (ZCOMP) should include R1 through C2 as noted for either filter type, of the same style and value as their counterparts in the forward path. The effects of a ZCOMP network on the THD + N performance of two 1 kHz HP filters is illustrated in Figure 46. One filter (A) is the example shown in Figure 44a (Curves A1 and A2), while the second (B) uses RC values scaled 10 times upward in impedance (Curves B1 and B2). Both filters operate with a 2 V rms input, 18 V supplies, 100 k loading, and analyzer bandwidth of 80 kHz.
A1 0.001 B2 A2
0.0001 20 100 1k FREQUENCY - Hz 10 k 20k
Figure 46. THD + N (%) vs. Frequency for Various 1 kHz HP Active Filters Illustrating the Effects of the ZCOMP Network
Curves A1 and B1 show performance with ZCOMP shorted, while curves A2 and B2 illustrate operation with ZCOMP active. For the "A" example values, distortion in the pass band of 1 kHz-20 kHz is below 0.001% compensated, and slightly higher uncompensated. With the higher impedance "B" network, there is a much greater difference between compensated and uncompensated responses, underscoring the sensitivity to higher impedances. Although the positive effect of ZCOMP is seen for both "A" and "B" cases, there is a buffering effect which takes place with lower impedances. As case "A" shows, when using larger capacitance values in the source, the amplifier's nonlinear C-V input characteristics have less effect on the signal. Thus, to minimize the necessity for the complete ZCOMP compensation, effective filter designs should use the lowest capacitive impedances practical, with an 0.01 F lower value limit as a goal for lowest distortion (while lower values can certainly be used, they may suffer higher distortion without the use of full compensation). Since most designs are likely to use low relative impedances for reasons of low noise and offset, the effects of CM distortion may or may not actually be apparent to a given application.
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REV. 0
OP176
97 EP
I1 98 R5 CM2 -IN 2 IOS 1 +IN CM1 5 C2 6 CIN D1 36 D2 EN 3 EOS Q1 7
4 R6 8 Q2 VN1 DN1 10 VN2 DN2 11 VN4 VN3 DN3 13 DN4 14 CN1 VN6 VN5 DN5 16 DN6 17 C1 9 35 12 15
98
R3
R4
EM
97 V2 19 D3 21 R9 G1 98 R7 C3 G2 R8 22 G3 C4 R10 C5 G4 R11 C6 E2 23 24 25 R12 R13 98 26 C7
D4 20 V3 51
EREF
99 D7 R15 28 27 31 D6 R16 C9 D9 G6 50 G7 32 33 G9 D10 V5 F2 R18 ISY D5 30 D8 G8 V4 F1 L2 R17
29
34
G5 98
R14
C8
Figure 47. OP176 Spice Model Schematic
REV. 0
-17-
OP176
OP176 SPICE Model
* * Node Assignments * Noninverting Input * | Inverting Input * | | Positive Supply * | | | Negative Supply * | | | | Output * | | | | | * | | | | | .SUBCKT OP176 1 2 99 50 34 * * INPUT STAGE & POLE AT 100 MHz * R3 5 51 2.487 R4 6 51 2.487 CIN 1 2 3.7E-12 CM1 1 98 7.5E-12 CM2 2 98 7.5E-12 C2 5 6 320E-12 I1 97 4 100E-3 IOS 1 2 1E-9 EOS 9 3 POLY(1) (26,28) 0.2E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 1.970 R6 8 4 1.970 D1 2 36 DZ D2 1 36 DZ EN 3 1 (10,0) 1 GN1 0 2 (13,0) 1E-3 GN2 0 1 (16,0) 1E-3 * EREF 98 0 (28,0) 1 EP 97 0 (99,0) 1 EM 51 0 (50,0) 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 * * GAIN STAGE & DOMINANT POLE AT 32 Hz * R7 18 98 1.243E6 C3 18 98 4E-9 G1 98 18 (5,6) 4.021E-1 V2 97 19 1.35 V3 20 51 1.35 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz * R8 21 98 1E3 R9 21 22 1.25E3 C4 22 98 47.2E-12 G2 98 21 (18,28) 1E-3 * * POLE AT 100 MHz * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 (21,28) 1 * * POLE AT 100 MHz * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 (23,28) 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz * R12 25 26 1E6 C7 25 26 60E-12 R13 26 98 1 E2 25 98 POLY(2) (1,98) (2,98) 0 2.50 2.50 * * POLE AT 100 MHz * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 (24,28) 1 * * OUTPUT STAGE * R15 28 99 58.333E3 R16 28 50 58.333E3 C9 28 50 1E-6 ISY 99 50 1.743E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 (27,29) 10E-3 G7 33 50 (29,27) 10E-3 G8 29 99 (99,27) 10E-3 G9 50 29 (27,50) 10E-3 V4 30 29 1.74 V5 29 31 1.74 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=5E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1) .ENDS OP176
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REV. 0
OP176
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
8 PIN 1 1
5 0.280 (7.11) 0.240 (6.10) 4
0.430 (10.92) 0.348 (8.84) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.130 (3.30) MIN SEATING PLANE
0.015 (0.381) 0.008 (0.204)
0.022 (0.558) 0.014 (0.356)
0.070 (1.77) 0.045 (1.15)
8-Lead Narrow-Body SO (SO-8)
8
5 0.1574 (4.00) 0.1497 (3.80)
PIN 1 1 4
0.2440 (6.20) 0.2284 (5.80)
0.1968 (5.00) 0.1890 (4.80) 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 8 0
0.0196 (0.50) x 45 0.0099 (0.25)
0.0098 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
REV. 0
-19-
-20-
C1878-10-1/94
PRINTED IN U.S.A.
OP176
FOR CATALOG
ORDERING GUIDE
Model OP176GP OP176GS OP176GSR OP176GBC
Temperature Range -40C to +85C -40C to +85C -40C to +85C +25C
Package Description 8-Pin Plastic DIP 8-Pin SOIC SO-8 Reel, 2500 Pieces DICE
Package Option* N-8 SO-8
*For outline information see Package Information section.
REV. 0
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